1. Field of the Invention
The present invention relates to memory circuits composed of semiconductor elements and, more particularly, to a memory circuit using field effect transistors.
2. Description of the Prior Art
In a dynamic type random access memory (DRAM) composed of MOS field-effect transistors (MOSTs), the so-called "multi-strobe addressing" technique is frequently used. According to this technique, the DRAM receives row address signals through address input terminals in response to a row address strobe signal (RAS) and column address signals through the same address input terminals in response to a column address strobe signal (CAS). The multi-strobe addressing technique is disclosed in detail in U.S. Pat. No. 3,969,706. Such a memory has a row timing signal generator which generates a control signal for controlling a peripheral circuit for the row selection such as a row decoder and controlling a sense amplifier in response to the row address strobe signal, a column timing signal generator which responds to the column address strobe signal and the output from the row timing signal generator to generate a control signal controlling a column decoder, a column selector, a data input-output circuit, and a read-write control signal generator which responds to the column address strobe signal and a read-write signal (WE) to generate the read-write control signal controlling the data input-output circuit between read and write modes. Since the read-write control signal is generated in response to the column strobe signal, it has been difficult to bring the state of the memory immediately into the write mode even when the read-write signal is turned to a write level designating the write operation, and therefore the speed of the write operation is inevitally slow.